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ECBS
2007
IEEE
145views Hardware» more  ECBS 2007»
15 years 1 months ago
Automatic Verification and Performance Analysis of Time-Constrained SysML Activity Diagrams
We present in this paper a new approach for the automatic verification and performance analysis of SysML activity diagrams. Since timeliness is important in the design and analysi...
Yosr Jarraya, Andrei Soeanu, Mourad Debbabi, Fawzi...
CADE
2008
Springer
15 years 10 months ago
Exploring Model-Based Development for the Verification of Real-Time Java Code
Many safety- and security-critical systems are real-time systems and, as a result, tools and techniques for verifying real-time systems are extremely important. Simulation and test...
Niusha Hakimipour, Paul A. Strooper, Roger Duke
ICCD
1999
IEEE
91views Hardware» more  ICCD 1999»
15 years 2 months ago
Architectural Synthesis of Timed Asynchronous Systems
ions", in IEEE Transactions on CAD of VLSI, 25(3):403-412, March, 2006. , E. Mercer, C. Myers, "Modular Verification of Timed Systems Using Automatic Abstraction" in...
Brandon M. Bachman, Hao Zheng, Chris J. Myers
ADAEUROPE
2008
Springer
14 years 11 months ago
On the Timed Automata-Based Verification of Ravenscar Systems
The Ravenscar profile for Ada enforces several restrictions on the usage of general-purpose tasking constructs, thereby facilitating most analysis tasks and in particular functiona...
Iulian Ober, Nicolas Halbwachs
ENTCS
2006
142views more  ENTCS 2006»
14 years 9 months ago
Predicate Diagrams for the Verification of Real-Time Systems
We propose a format of predicate diagrams for the verification of real-time systems. We consider systems that are defined as extended timed graphs, a format that combines timed au...
Eun-Young Kang, Stephan Merz