521 search results - page 18 / 105 » Timing Verification Using HDTV |
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CAV
2001
Springer
15 years 1 months ago
2001
Springer
We consider the randomized consensus protocol of Aspnes and Herlihy for achieving agreement among N asynchronous processes that communicate via read/write shared registers. The alg...
CODES
2008
IEEE
14 years 11 months ago
2008
IEEE
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
FMSD
2006
14 years 9 months ago
2006
Two base algorithms are known for reachability verification over timed automata. They are called forward and backwards, and traverse the automata edges using either successors or p...
FPGA
2005
ACM
15 years 3 months ago
2005
ACM
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...
ISQED
2003
IEEE
15 years 3 months ago
2003
IEEE
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...