521 search results - page 22 / 105 » Timing Verification Using HDTV |
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FDL
2003
IEEE
15 years 3 months ago
2003
IEEE
Reconfigurable Systolic Arrays are a generalization of Systolic Arrays where node operations and interconnections can be redefined even at run time. This flexibility increases the...
HYBRID
2007
Springer
15 years 1 months ago
2007
Springer
Abstract. In this paper, we propose a new approach for formal verification of hybrid systems. To do so, we present a new refinement proof technique, a weak refinement using step in...
EPK
2006
14 years 11 months ago
2006
Abstract: Event-driven Process Chains (EPCs) are a commonly used modelling technique for design and documentation of business processes. Although EPCs have an easy-to-understand no...
CSREAESA
2004
14 years 11 months ago
2004
In this paper we present an algorithm for automatic extraction of system behavior from a structural Verilog specification. The algorithm generates a series-parallel poset expressi...
DAC
2000
ACM
15 years 10 months ago
2000
ACM
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...