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ICCAD
2003
IEEE
205views Hardware» more  ICCAD 2003»
15 years 3 months ago
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
Aseem Agarwal, David Blaauw, Vladimir Zolotov
ASPDAC
2006
ACM
137views Hardware» more  ASPDAC 2006»
15 years 3 months ago
Parameterized block-based non-gaussian statistical gate timing analysis
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
DAC
2004
ACM
15 years 10 months ago
STAC: statistical timing analysis with correlation
Current technology trends have led to the growing impact of both inter-die and intra-die process variations on circuit performance. While it is imperative to model parameter varia...
Jiayong Le, Xin Li, Lawrence T. Pileggi
VTC
2006
IEEE
117views Communications» more  VTC 2006»
15 years 3 months ago
Design and Implementation of Robust Time/Frequency Offset Tracking Algorithm for MIMO-OFDM Receivers
— In this paper, the robust time and frequency offset tracking algorithms and architecture for high throughput wireless local area network (WLAN) systems are presented. The desig...
Il-Gu Lee, Heejung Yu, Eunyoung Choi, Jungbo Son, ...
DAC
2006
ACM
15 years 10 months ago
Criticality computation in parameterized statistical timing
Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult ...
Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswa...