521 search results - page 7 / 105 » Timing Verification Using HDTV |
DAC
1994
ACM
15 years 1 months ago
1994
ACM
Functional and timing verification are currently the bottlenecks in many design efforts. Simulation and emulation are extensively used for verification. Formal verification is now...
CORR
2010
Springer
14 years 7 months ago
2010
Springer
This paper motivates the need for a formalism for the modelling and analysis of dynamic reconfiguration of dependable real-time systems. We present requirements that the formalism ...
89
Voted
CORR
2008
Springer
14 years 9 months ago
2008
Springer
This article introduces a fully automated verification technique that permits to analyze real-time systems described using a continuous notion of time and a mixture of operational...
115
click to vote
REFSQ
2010
Springer
2010
Springer
Challenges in Aligning Requirements Engineering and Verification in a Large-Scale Industrial Context
14 years 7 months ago
[Context and motivation] When developing software, coordination between different organizational units is essential in order to develop a good quality product, on time and within b...
120
click to vote
DLT
2009
14 years 7 months ago
2009
Abstract. Temporal logics are a well investigated formalism for the specification and verification of reactive systems. Using formal verification techniques, we can ensure the corr...