521 search results - page 94 / 105 » Timing Verification Using HDTV |
DAC
2006
ACM
15 years 10 months ago
2006
ACM
Simulation and verification using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems. The synchronous dat...
ICNP
1999
IEEE
15 years 2 months ago
1999
IEEE
In this paper we present a new approach for the automated mapping of formal descriptions into activity thread implementations. Our approach resolves semantic conflicts by reorderi...
ATVA
2006
Springer
14 years 11 months ago
2006
Springer
Abstract. In this paper, we give an algorithm for fault-tolerant proactive leader election in asynchronous shared memory systems, and later its formal verification. Roughly speakin...
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DT
2006
14 years 9 months ago
2006
process: Designers must define higher abstraction levels that allow system modeling. They must use description languages that handle both hardware and software components to descri...
ASE
2002
14 years 9 months ago
2002
This paper describes a specialized interface to PVS called TAME (Timed Automata Modeling Environment) which provides automated support for proving properties of I/O automata. A maj...