521 search results - page 9 / 105 » Timing Verification Using HDTV |
DAC
2005
ACM
14 years 11 months ago
2005
ACM
This paper describes a novel technique called Embedded Test-bench Control (ETC), extensively used in the verification of Tensilica’s latest configurable processor. Conventional ...
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
Choosing the right methodology is a significant step towards successful VLSI designs. Traditional methodologies and tools are no longer adequate to handle large and complex design...
ENTCS
2002
14 years 9 months ago
2002
We present a new approach to the modelling of time constrained systems. It is based on untimed high-level Petri nets using the concept of causal time. With this concept, the progr...
FPL
2006
Springer
15 years 1 months ago
2006
Springer
This paper provides a realistic case study of using the previously introduced SIMPPL system architectural model, which fixes the physical interface and communication protocols bet...
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CAV
2007
Springer
15 years 1 months ago
2007
Springer
Abstract. In this paper, we describe the features of the Timed Abstract State Machine toolset. The toolset implements the features of the Timed Abstract State Machine (TASM) langua...