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90
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ICCAD
2005
IEEE
133views Hardware» more  ICCAD 2005»
15 years 9 months ago
Gate sizing using incremental parameterized statistical timing analysis
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
Matthew R. Guthaus, Natesan Venkateswaran, Chandu ...
88
Voted
ICCD
1995
IEEE
85views Hardware» more  ICCD 1995»
15 years 4 months ago
A high-performance asynchronous SCSI controller
We describe thedesign of a high performance asynchronous SCSI Small Computer Systems Interface controller data path and the associated control circuits. The data path is an asyn...
Kenneth Y. Yun, David L. Dill
95
Voted
ADAEUROPE
2008
Springer
15 years 2 months ago
On the Timed Automata-Based Verification of Ravenscar Systems
The Ravenscar profile for Ada enforces several restrictions on the usage of general-purpose tasking constructs, thereby facilitating most analysis tasks and in particular functiona...
Iulian Ober, Nicolas Halbwachs
VTC
2010
IEEE
174views Communications» more  VTC 2010»
14 years 11 months ago
Multiple-Relay Aided Distributed Turbo Coding Assisted Differential Unitary Space-Time Spreading for Asynchronous Cooperative Ne
—This paper proposes a cooperative space-time coding (STC) protocol, amalgamating the concepts of asynchronous cooperation, non-coherent detection as well as Distributed Turbo Co...
Shinya Sugiura, Soon Xin Ng, Lingkun Kong, Sheng C...
RTS
2008
131views more  RTS 2008»
15 years 17 hour ago
Formal verification of multitasking applications based on timed automata model
The aim of this paper is to show, how a multitasking application running under a real-time operating system compliant with an OSEK/VDX standard can be modeled by timed automata. Th...
Libor Waszniowski, Zdenek Hanzálek