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DATE
2010
IEEE
119views Hardware» more  DATE 2010»
15 years 22 days ago
Practical Monte-Carlo based timing yield estimation of digital circuits
—The advanced sampling and variance reduction techniques as efficient alternatives to the slow crude-MC method have recently been adopted for the analysis of timing yield in dig...
Javid Jaffari, Mohab Anis
127
Voted
FMCO
2003
Springer
114views Formal Methods» more  FMCO 2003»
15 years 5 months ago
Synchronous Closing and Flow Analysis for Model Checking Timed Systems
Abstract. Formal methods, in particular model checking, are increasingly accepted as integral part of system development. With large software systems beyond the range of fully auto...
Natalia Ioustinova, Natalia Sidorova, Martin Steff...
109
Voted
ICCAD
2003
IEEE
205views Hardware» more  ICCAD 2003»
15 years 5 months ago
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
Aseem Agarwal, David Blaauw, Vladimir Zolotov
95
Voted
ASYNC
1998
IEEE
71views Hardware» more  ASYNC 1998»
15 years 4 months ago
Towards Asynchronous A-D Conversion
Analogue to digital (A-D) converters with a xed conversion time are subject to errors due to metastability. These errors will occur in all converter designs with a bounded time fo...
D. J. Kinniment, Alexandre Yakovlev, Fei Xia, B. G...
124
Voted
CMSB
2007
Springer
15 years 6 months ago
Context Sensitivity in Logical Modeling with Time Delays
For modeling and analyzing regulatory networks based on qualitative information and possibly additional temporal constraints, approaches using hybrid automata can be very helpful. ...
Heike Siebert, Alexander Bockmayr