435 search results - page 26 / 87 » Timing analysis of asynchronous circuits using timed automat... |
107
Voted
DATE
2009
IEEE
15 years 7 months ago
2009
IEEE
— Statistical static timing analysis deals with the increasing variations in manufacturing processes to reduce the pessimism in the worst case timing analysis. Because of the cor...
ICCAD
1994
IEEE
15 years 4 months ago
1994
IEEE
- This paper addresses the problem of true delay estimation during high level design. The existing delay estimation techniques either estimate the topological delay of the circuit ...
ITC
1996
IEEE
15 years 4 months ago
1996
IEEE
A 25k gate Test Chip was designed and manufactured to evaluate different test methods for scan-designed circuits. The design of the chip, the experiment, and preliminary experimen...
121
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DAC
2008
ACM
16 years 1 months ago
2008
ACM
Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
97
Voted
ASYNC
2006
IEEE
15 years 6 months ago
2006
IEEE
A fast asynchronous shift register is used as the serializer and de-serializer in a novel bit-serial on-chip communication link. The link employs two-phase transition-based LEDR e...