435 search results - page 29 / 87 » Timing analysis of asynchronous circuits using timed automat... |
132
Voted
PTS
2008
15 years 1 months ago
2008
The state space explosion due to concurrency and timing constraints of concurrent real-time systems (CRTS) presents significant challenges to the verification engineers. In this pa...
118
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CBSE
2005
Springer
15 years 6 months ago
2005
Springer
We consider a class of component-based software models with interaction style of buffered asynchronous message passing between components with ports, represented by UML-RT. After ...
104
Voted
DDECS
2009
IEEE
15 years 7 months ago
2009
IEEE
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...
115
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DAC
2007
ACM
16 years 1 months ago
2007
ACM
An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is...
DATE
2004
IEEE
15 years 4 months ago
2004
IEEE
This paper proposes a new hierarchical circuit modeling and simulation technique in s-domain for linear analog circuits. The new algorithm can perform circuit complexity reduction...