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91
Voted
VLSID
2005
IEEE
16 years 27 days ago
2005
IEEE
Synchronous design methods have intrinsic performance overheads due to their use of the global clock and timing assumptions. In future manufacturing processes not only may it beco...
100
Voted
NOTERE
2010
14 years 11 months ago
2010
Abstract—We review the issues with the conception of realtime event based applications and propose an event manager component design. We start from the design proposed by the Rea...
92
Voted
DATE
2009
IEEE
15 years 7 months ago
2009
IEEE
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...
129
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GLVLSI
2006
IEEE
15 years 6 months ago
2006
IEEE
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...
108
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SAC
2006
ACM
15 years 6 months ago
2006
ACM
: In chip design, one of the main objectives is to decrease its clock cycle; however, the existing approaches to timing analysis under uncertainty are based on fundamentally restri...