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ICCAD
2005
IEEE
176views Hardware» more  ICCAD 2005»
15 years 9 months ago
Statistical gate sizing for timing yield optimization
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
Debjit Sinha, Narendra V. Shenoy, Hai Zhou
123
Voted
NFM
2011
223views Formal Methods» more  NFM 2011»
14 years 7 months ago
opaal: A Lattice Model Checker
Abstract. We present a new open source model checker, opaal, for automatic verification of models using lattice automata. Lattice automata allow the users to incorporate abstracti...
Andreas Engelbredt Dalsgaard, René Rydhof H...
91
Voted
ETFA
2006
IEEE
15 years 6 months ago
Optimizing Quality of Control in Networked Automation Systems using Probabilistic Models
New technological trends lead to the increasing use of network technologies in automation. Especially the Ethernet with TCP/IP and wireless networks find growing acceptance. The r...
Jürgen Greifeneder, Georg Frey
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
15 years 5 months ago
Aging-resilient design of pipelined architectures using novel detection and correction circuits
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
Hamed F. Dadgour, Kaustav Banerjee
110
Voted
ECAI
2010
Springer
15 years 21 days ago
Brothers in Arms? On AI Planning and Cellular Automata
AI Planning is concerned with the selection of actions towards achieving a goal. Research on cellular automata (CA) is concerned with the question how global behaviours arise from ...
Jörg Hoffmann, Nazim Fatès, Héc...