435 search results - page 36 / 87 » Timing analysis of asynchronous circuits using timed automat... |
124
Voted
FM
2009
Springer
15 years 5 months ago
2009
Springer
We study a clock synchronization protocol for the Chess WSN. First, we model the protocol as a network of timed automata and verify various instances using the Uppaal model checker...
104
Voted
ASPDAC
2006
ACM
15 years 6 months ago
2006
ACM
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
ICCAD
2006
IEEE
15 years 9 months ago
2006
IEEE
Statistical Static Timing Analysis has received wide attention recently and emerged as a viable technique for manufacturability analysis. To be useful, however, it is important th...
106
Voted
ICCAD
2007
IEEE
15 years 6 months ago
2007
IEEE
Modeling the effect of coupling noise on circuit delay is a key issue in static timing analysis (STA) and involves the “victimaggressor alignment” problem. As delay-noise depe...
DAC
2008
ACM
16 years 1 months ago
2008
ACM
This paper introduces an accurate and efficient electrical analysis of logic gates modeled as Multiple Voltage Threshold Models (MVTM) loaded by the associated interconnect. MVTMs...