435 search results - page 42 / 87 » Timing analysis of asynchronous circuits using timed automat... |
87
Voted
EUSFLAT
2003
15 years 1 months ago
2003
Industrial processes can be often modelled using Petri nets. If all the process variables (or events) are assumed to be twovalued signals, then it is possible to obtain a hardware...
ICCAD
1999
IEEE
15 years 4 months ago
1999
IEEE
Available techniques for testing core-based systems-on-a-chip (SOCs) do not provide a systematic means for synthesising low-overhead test architectures and compact test solutions....
84
Voted
DATE
2006
IEEE
15 years 6 months ago
2006
IEEE
— In this paper, we present an analysis methodology to compute circuit node sensitivity due to charged particle induced delay (timing) errors, Soft Delay Errors (SDE). We define...
117
Voted
WCET
2010
14 years 10 months ago
2010
To take full advantage of the increasingly used shared-memory multicore architectures, software algorithms will need to be parallelized over multiple threads. This means that thre...
ITC
2003
IEEE
15 years 5 months ago
2003
IEEE
A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of...