435 search results - page 46 / 87 » Timing analysis of asynchronous circuits using timed automat... |
ATS
2000
IEEE
15 years 4 months ago
2000
IEEE
We present a new test generation procedure for sequential circuits using newly traversed state and newly detected fault information obtained between successive iterations of vecto...
119
Voted
ICCAD
1999
IEEE
15 years 4 months ago
1999
IEEE
We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes al...
103
Voted
WISES
2004
15 years 1 months ago
2004
-- Debugging software that runs on highly integrated System-on-Chip devices is complicated because conventional debug tools (like traditional In-Circuit Emulators and Logic Analyze...
128
Voted
RTSS
2005
IEEE
15 years 6 months ago
2005
IEEE
Recently there has been a growing interest in models and methods targeted towards the (co)design of stream processing applications; e.g. those for audio/video processing. Streams ...
115
Voted
MJ
2007
14 years 12 months ago
2007
With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes...