435 search results - page 52 / 87 » Timing analysis of asynchronous circuits using timed automat... |
ICCAD
2003
IEEE
15 years 9 months ago
2003
IEEE
This paper presents an efficient method to reduce complexities of a linear network in s-domain. The new method works on circuit matrices directly and reduces the circuit complexi...
74
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DELTA
2006
IEEE
15 years 6 months ago
2006
IEEE
— Design, Verification and Test of integrated circuits with millions of gates put strong requirements on design time, test volume, test application time, test speed and diagnost...
138
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NOCS
2008
IEEE
15 years 6 months ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
102
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DAC
2007
ACM
16 years 1 months ago
2007
ACM
Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability challenges in nano-scale technology. This paper presents an efficient technique to characte...
134
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CAV
2000
Springer
15 years 4 months ago
2000
Springer
Address: Abstraction, Composition, Symmetry, and a Little Deduction: The Remedies to State Explosion . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A. Pnueli Invited Address...