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FPGA
2007
ACM
142views FPGA» more  FPGA 2007»
15 years 6 months ago
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
N. Pete Sedcole, Peter Y. K. Cheung
110
Voted
FDL
2007
IEEE
15 years 4 months ago
Towards Assertion Based Verification of Analog and Mixed Signal Designs Using PSL
Abstract-- Analog and Mixed Signal (AMS) designs are important integrated systems that link digital circuits to the analog world. Following the success of PSL verification methodol...
Ghiath Al Sammane, Mohamed H. Zaki, Zhi Jie Dong, ...
87
Voted
DAC
2003
ACM
16 years 1 months ago
Temporofunctional crosstalk noise analysis
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. This paper proposes a method of characterizing correlation of signal tra...
Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H...
DATE
2007
IEEE
138views Hardware» more  DATE 2007»
15 years 6 months ago
An ADC-BiST scheme using sequential code analysis
This paper presents a built-in self-test (BiST) scheme for analog to digital converters (ADC) based on a linear ramp generator and efficient output analysis. The proposed analysi...
Erdem Serkan Erdogan, Sule Ozev
ASYNC
2003
IEEE
100views Hardware» more  ASYNC 2003»
15 years 5 months ago
Congestion and Starvation Detection in Ripple FIFOs
High-speed asynchronous ripple FIFOs may be easily embedded in synchronous environments and can elegantly handle the problem of forwarding data between clock domains. In cases whe...
William S. Coates, Robert J. Drost