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ISPD
1998
ACM
244views Hardware» more  ISPD 1998»
15 years 4 months ago
Analysis, reduction and avoidance of crosstalk on VLSI chips
As chip size and design density increase, coupling effects (crosstalk) between signal wires become increasingly critical to on–chip timing and even functionality. A method is pr...
Tilmann Stöhr, Markus Alt, Asmus Hetzel, J&uu...
91
Voted
ICCAD
2006
IEEE
125views Hardware» more  ICCAD 2006»
15 years 9 months ago
Leveraging protocol knowledge in slack matching
Stalls, due to mis-matches in communication rates, are a major performance obstacle in pipelined circuits. If the rate of data production is faster than the rate of consumption, t...
Girish Venkataramani, Seth Copen Goldstein
82
Voted
IPPS
2006
IEEE
15 years 6 months ago
Parallelization and performance characterization of protein 3D structure prediction of Rosetta
The prediction of protein 3D structure has become a hot research area in the post-genome era, through which people can understand a protein’s function in health and disease, exp...
Wenlong Li, Tao Wang, Eric Li, D. Baker, Li Jin, S...
DATE
2002
IEEE
111views Hardware» more  DATE 2002»
15 years 5 months ago
A Linear-Centric Modeling Approach to Harmonic Balance Analysis
In this paper we propose a new harmonic balance simulation methodology based on a linear-centric modeling approach. A linear circuit representation of the nonlinear devices and as...
Peng Li, Lawrence T. Pileggi
ISCAS
2005
IEEE
114views Hardware» more  ISCAS 2005»
15 years 6 months ago
Performance analysis by topology indexed lookup tables
— Accurate analysis of VLSI interconnects is essential to the performance-driven synthesis and layout of integrated circuits. Existing techniques are based on either simulation, ...
P. Agarwal, A. Vidyarthi, Patrick H. Madden