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FORMATS
2003
Springer
15 years 3 months ago
Performance Analysis of Probabilistic Timed Automata Using Digital Clocks
Probabilistic timed automata, a variant of timed automata extended with discrete probability distributions, is a specification formalism suitable for describing both nondeterminis...
Marta Z. Kwiatkowska, Gethin Norman, David Parker,...
ICCAD
1999
IEEE
84views Hardware» more  ICCAD 1999»
15 years 2 months ago
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ens...
Jordi Cortadella, Michael Kishinevsky, Steven M. B...
ASYNC
2005
IEEE
118views Hardware» more  ASYNC 2005»
15 years 3 months ago
Modeling and Verifying Circuits Using Generalized Relative Timing
We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not ...
Sanjit A. Seshia, Randal E. Bryant, Kenneth S. Ste...
ICCAD
1998
IEEE
83views Hardware» more  ICCAD 1998»
15 years 1 months ago
Lazy transition systems: application to timing optimization of asynchronous circuits
This paper introduces Lazy Transitions Systems (LzTSs). The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a transition system. LzT...
Jordi Cortadella, Michael Kishinevsky, Alex Kondra...
ASYNC
2005
IEEE
132views Hardware» more  ASYNC 2005»
15 years 3 months ago
High Level Synthesis of Timed Asynchronous Circuits
This paper proposes applying a logic synthesis approach to high level synthesis from SpecC specifications to timed asynchronous gate-level circuits. The state-based logic synthes...
Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, C...