435 search results - page 61 / 87 » Timing analysis of asynchronous circuits using timed automat... |
124
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GLVLSI
2003
IEEE
15 years 5 months ago
2003
IEEE
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...
122
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TCS
2008
15 years 9 days ago
2008
This paper studies a novel paradigm for learning formal languages from positive and negative examples which consists of mapping strings to an appropriate highdimensional feature s...
115
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ICCAD
1995
IEEE
15 years 4 months ago
1995
IEEE
: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly...
120
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VTS
2000
IEEE
15 years 4 months ago
2000
IEEE
The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...
88
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ASPDAC
2006
ACM
15 years 6 months ago
2006
ACM
— Process variations in digital circuits make sequential circuit timing validation an extremely challenging task. In this paper, a Statistical Bellman-Ford (SBF) algorithm is pro...