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ISQED
2010
IEEE
128views Hardware» more  ISQED 2010»
15 years 3 months ago
Soft error rate determination for nanoscale sequential logic
We analyze the neutron induced soft error rate (SER) by modeling induced error pulse using two parameters, occurrence frequency and probability density function for the pulse widt...
Fan Wang, Vishwani D. Agrawal
VLSID
2002
IEEE
160views VLSI» more  VLSID 2002»
15 years 10 months ago
PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis
Predictive delay analysis is presented for a representative CMOS inverter with submicron device size using PREDICTMOS MOSFET model. As against SPICE, which adopts a time consuming...
A. B. Bhattacharyya, Shrutin Ulman
64
Voted
PIMRC
2008
IEEE
15 years 4 months ago
BER analysis of single-carrier MPAM in the presence of ADC quantization noise
— Noisy radio frequency (RF) circuits tend to degrade the system performance, especially in high frequency communication systems. The performance analysis of such systems is norm...
Umar H. Rizvi, Gerard J. M. Janssen, Jos H. Weber
83
Voted
ISLPED
1997
ACM
114views Hardware» more  ISLPED 1997»
15 years 2 months ago
Cycle-accurate macro-models for RT-level power analysis
 In this paper we present a methodology and techniques for generating cycle-accurate macro-models for RTlevel power analysis. The proposed macro-model predicts not only...
Qinru Qiu, Qing Wu, Massoud Pedram, Chih-Shun Ding
TCAD
2002
99views more  TCAD 2002»
14 years 9 months ago
Analysis of on-chip inductance effects for distributed RLC interconnects
This paper introduces an accurate analysis of on-chip inductance effects for distributed interconnects that takes the effect of both the series resistance and the output parasitic ...
Kaustav Banerjee, Amit Mehrotra