Advanced process technologies call for a proactive consideration of process variations in design to ensure high parametric timing yield. Despite of its popular use in almost any h...
Statistical static timing analysis (SSTA) has become a key method for analyzing the effect of process variation in aggressively scaled CMOS technologies. Much research has focused...
In the nanometer manufacturing region, process variation causes significant uncertainty for circuit performance verification. Statistical static timing analysis (SSTA) is thus dev...
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class o...
In this paper we present a simple and general new No Free Lunch-like result that applies to revisiting algorithms searching arbitrary problem sets. We begin by unifying the assumpt...