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ASPDAC
2007
ACM
119views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng,...
CGF
2010
98views more  CGF 2010»
14 years 9 months ago
Image Synthesis for Branching Structures
We present a set of techniques for the synthesis of artificial images that depict branching structures like rivers, cracks, lightning, mountain ranges, or blood vessels. The centr...
Dominik Sibbing, Darko Pavic, Leif Kobbelt
AIPS
2000
14 years 11 months ago
Vision-Servoed Localization and Behavior-Based Planning for an Autonomous Quadruped Legged Robot
Planning for real robots to act in dynamic and uncertain environments is a challenging problem. A complete model of the world is not viable and an integration of deliberation and ...
Manuela M. Veloso, Elly Winner, Scott Lenser, Jame...
ICCAD
2000
IEEE
188views Hardware» more  ICCAD 2000»
15 years 2 months ago
Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method
— Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral l...
Sungpack Hong, Taewhan Kim
87
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SAMOS
2007
Springer
15 years 3 months ago
An Evolutionary Approach to Area-Time Optimization of FPGA designs
—This paper presents a new methodology based on evolutionary multi-objective optimization (EMO) to synthesize multiple complex modules on programmable devices (FPGAs). It starts ...
Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Paler...