118 search results - page 18 / 24 » Timing constraint specification and synthesis in behavioral ... |
ISQED
2006
IEEE
15 years 3 months ago
2006
IEEE
Unlike their hard realtime counterparts, soft realtime applications are only expected to guarantee their ”expected delay” over input data space. This paradigm shift calls for ...
106
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EON
2008
14 years 11 months ago
2008
We reuse here the framework, the setting, and the semantic modelling for the automated synthesis of the SWS Challenge Mediator presented in the companion paper [5], and show how to...
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
68
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ICCAD
1994
IEEE
15 years 1 months ago
1994
IEEE
Language containment is a method for design verification that involves checking if the behavior of the system to be verified is a subset of the behavior of the specifications (pro...
ASPDAC
1995
ACM
15 years 1 months ago
1995
ACM
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...