118 search results - page 6 / 24 » Timing constraint specification and synthesis in behavioral ... |
ICCAD
1992
IEEE
15 years 1 months ago
1992
IEEE
This paper presents a comprehensive timing model for behavioral-level specifications and algorithms for timing analysis in high-level synthesis. It is based on a timing network wh...
ASPDAC
2008
ACM
14 years 11 months ago
2008
ACM
A major trend in a modern system-on-chip design is a growing system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architec...
ASPDAC
2009
ACM
15 years 4 months ago
2009
ACM
— As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. In the presence of process variations, wo...
CONCUR
2006
Springer
15 years 1 months ago
2006
Springer
Abstract. We consider the control problem for timed automata against specifications given as MTL formulas. The logic MTL is a linear-time timed temporal logic which extends LTL wit...
86
Voted
VLSID
2007
IEEE
15 years 10 months ago
2007
IEEE
We present minimization methodologies and an algorithm for simultaneous scheduling, binding, and allocation for the reduction of total power and power fluctuation during behaviora...