58 search results - page 6 / 12 » Timing driven power gating in high-level synthesis |
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ISQED
2006
IEEE
15 years 3 months ago
2006
IEEE
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...
75
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ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
GW
2005
Springer
15 years 3 months ago
2005
Springer
Abstract. The work described in this abstract presents a roadmap towards the creation and specification of a virtual humanoid capable of performing expressive gestures in real tim...
ISORC
2005
IEEE
15 years 3 months ago
2005
IEEE
As complexity of real-time embedded software grows, it is desirable to use formal verification techniques to achieve a high level of assurance. We discuss application of model-ch...
ASPDAC
2004
ACM
15 years 3 months ago
2004
ACM
This paper proposes a thread partitioning algorithm in low power high-level synthesis. The algorithm is applied to high-level synthesis systems. In the systems, we can describe pa...