58 search results - page 9 / 12 » Timing driven power gating in high-level synthesis |
EH
2000
IEEE
15 years 2 months ago
2000
IEEE
Reconfigurable chips are integrated circuits whose internal connections can be programmed by the user to attend a specific application. Field Programmable Gate Arrays (FPGAs) and ...
VLSID
2006
IEEE
15 years 3 months ago
2006
IEEE
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
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TVLSI
2002
14 years 9 months ago
2002
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...
GLVLSI
2000
IEEE
15 years 2 months ago
2000
IEEE
In many applications such as high-level synthesis (HLS) and logic synthesis and possibly engineering change order (ECO) we would like to get fast and accurate estimations of diffe...
DAC
2000
ACM
15 years 10 months ago
2000
ACM
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...