57 search results - page 8 / 12 » Timing metrics for physical design of deep submicron technol... |
ICCAD
2005
IEEE
15 years 6 months ago
2005
IEEE
— Process variations cause significant timing uncertainty and yield degradation in deep sub-micron technologies. A solution to counter timing uncertainty is post-silicon clock t...
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CCECE
2006
IEEE
15 years 3 months ago
2006
IEEE
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
ASPDAC
2008
ACM
14 years 11 months ago
2008
ACM
Abstract-- Increasing delay and power variation are significant challenges to the designers as technology scales to the deep sub-micron (DSM) regime. Traditional module selection t...
ICCAD
2007
IEEE
15 years 6 months ago
2007
IEEE
— As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. As a result, a paradigm shift from determ...
ASPDAC
2005
ACM
15 years 3 months ago
2005
ACM
The progressive trend of fabrication technologies towards the nanometer regime has created a number of new physical design challenges for computer architects. Design complexity, u...