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» Timing model reduction for hierarchical timing analysis
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ICCD
1999
IEEE
91views Hardware» more  ICCD 1999»
15 years 6 months ago
Architectural Synthesis of Timed Asynchronous Systems
ions", in IEEE Transactions on CAD of VLSI, 25(3):403-412, March, 2006. , E. Mercer, C. Myers, "Modular Verification of Timed Systems Using Automatic Abstraction" in...
Brandon M. Bachman, Hao Zheng, Chris J. Myers
DSRT
2006
IEEE
15 years 8 months ago
Real Time P2P Network Simulation for Very Large Virtual Environment
The ever increasing speed of Internet connections has led to a point where it is actually possible for every end user to seamlessly share data on Internet. Peer-To-Peer (P2P) netw...
Romain Cavagna, Christian Bouville, Jér&oci...
POPL
2006
ACM
16 years 2 months ago
A hierarchical model of data locality
In POPL 2002, Petrank and Rawitz showed a universal result-finding optimal data placement is not only NP-hard but also impossible to approximate within a constant factor if P = NP...
Chengliang Zhang, Chen Ding, Mitsunori Ogihara, Yu...
ICML
2001
IEEE
16 years 2 months ago
Continuous-Time Hierarchical Reinforcement Learning
Hierarchical reinforcement learning (RL) is a general framework which studies how to exploit the structure of actions and tasks to accelerate policy learning in large domains. Pri...
Mohammad Ghavamzadeh, Sridhar Mahadevan
DAC
1999
ACM
16 years 2 months ago
Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
Chung-Ping Chen, Noel Menezes