4164 search results - page 4 / 833 » Timing model reduction for hierarchical timing analysis |
ASPDAC
2005
ACM
14 years 11 months ago
2005
ACM
— We develop a realizable circuit reduction to generate the interconnect macro-model for parasitic estimation in wideband applications. The inductance is represented by VPEC (vec...
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
This paper presents an efficient method to reduce complexities of a linear network in s-domain. The new method works on circuit matrices directly and reduces the circuit complexi...
ISQED
2006
IEEE
15 years 3 months ago
2006
IEEE
— A methodology is proposed for interdependent setup time and hold time characterization of sequential circuits. Integrating the methodology into an industrial sign-off static ti...
FLAIRS
2004
14 years 10 months ago
2004
er provides new techniques for abstracting the state space of a Markov Decision Process (MDP). These techniques extend one of the recent minimization models, known as -reduction, ...
ISORC
2008
IEEE
15 years 3 months ago
2008
IEEE
Conditional real-time task models, which are generalizations of periodic, sporadic, and multi-frame tasks, represent real world applications more accurately. These models can be c...