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» Timing model reduction for hierarchical timing analysis
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DATE
2007
IEEE
126views Hardware» more  DATE 2007»
15 years 3 months ago
WAVSTAN: waveform based variational static timing analysis
— We present a waveform based variational static timing analysis methodology. It is a timing paradigm that lies midway between convention static delay approximations and full dyn...
Saurabh K. Tiwary, Joel R. Phillips
ASPDAC
2005
ACM
118views Hardware» more  ASPDAC 2005»
14 years 11 months ago
Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction
This paper proposes a novel wideband modeling technique for high-performance RF passives and linear(ized) analog circuits. The new method is based on a recently proposed sdomain h...
Zhenyu Qi, Sheldon X.-D. Tan, Hao Yu, Lei He
ASPDAC
2006
ACM
157views Hardware» more  ASPDAC 2006»
15 years 3 months ago
Delay modeling and static timing analysis for MTCMOS circuits
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
Naoaki Ohkubo, Kimiyoshi Usami
COMPLIFE
2006
Springer
15 years 1 months ago
Set-Oriented Dimension Reduction: Localizing Principal Component Analysis Via Hidden Markov Models
We present a method for simultaneous dimension reduction and metastability analysis of high dimensional time series. The approach is based on the combination of hidden Markov model...
Illia Horenko, Johannes Schmidt-Ehrenberg, Christo...
ICCD
2004
IEEE
120views Hardware» more  ICCD 2004»
15 years 6 months ago
XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs
This paper describes XTalkDelay, an industrial-strength methodology and tool for measuring the impact of crosstalk on delays of paths in a design. The main cornerstone of XTalkDel...
Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwin...