93 search results - page 11 / 19 » Timing optimization of FPGA placements by logic replication |
83
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FPGA
2008
ACM
14 years 11 months ago
2008
ACM
This paper introduces a method of constructing random number generators from four of the basic primitives provided by FPGAs: Flip-Flips, Lookup-Tables, Shift Registers, and RAMs. ...
71
Voted
ERSA
2006
14 years 11 months ago
2006
Current FPGAs are heterogeneous partially reconfigurable architectures, consisting of several resource types, e. g., logic cells and embedded memory. By using partial reconfigurat...
106
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TCAD
2008
14 years 9 months ago
2008
The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the spe...
ICCAD
2008
IEEE
15 years 6 months ago
2008
IEEE
—When manufacturing nano-devices, defects are a certainty and reliability becomes a critical issue. Until now, the most pervasive methods used to address reliability, involve inj...
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
This work addresses the issue of design optimization for faulttolerant hard real-time systems. In particular, our focus is on the handling of transient faults using both checkpoin...