93 search results - page 14 / 19 » Timing optimization of FPGA placements by logic replication |
ASPDAC
2009
ACM
15 years 4 months ago
2009
ACM
Abstract— Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes...
ASPDAC
2005
ACM
15 years 3 months ago
2005
ACM
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
158
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ICDE
2006
IEEE
15 years 11 months ago
2006
IEEE
To use their pool of resources efficiently, distributed stream-processing systems push query operators to nodes within the network. Currently, these operators, ranging from simple...
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
In a realistic design flow, circuit and system optimizations must interact with physical aspects of the design. For example, improvements in timing and power may require replacing ...
51
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DAC
2008
ACM
15 years 10 months ago
2008
ACM
The creation of an FPGA requires extensive transistor-level design. This is necessary for both the final design, and during architecture exploration, when many different logic and...