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» Timing optimization of FPGA placements by logic replication
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FPGA
2007
ACM
163views FPGA» more  FPGA 2007»
15 years 3 months ago
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs
Boolean matching (BM) is a widely used technique in FPGA resynthesis and architecture evaluation. In this paper we present several improvements to the recently proposed SAT-based ...
Jason Cong, Kirill Minkovich
TVLSI
2008
119views more  TVLSI 2008»
14 years 9 months ago
Automatic Design of Reconfigurable Domain-Specific Flexible Cores
Reconfigurable hardware is ideal for use in Systems-on-a-Chip, as it provides both hardware-level performance and post-fabrication flexibility. However, any one architecture is ra...
Katherine Compton, Scott Hauck
DAC
2005
ACM
15 years 10 months ago
Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration
Many reconfigurable architectures offer partial dynamic configurability, but current system-level tools cannot guarantee feasible implementations when exploiting this feature. We ...
Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. D...
ISVLSI
2007
IEEE
184views VLSI» more  ISVLSI 2007»
15 years 3 months ago
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
BMCBI
2008
214views more  BMCBI 2008»
14 years 9 months ago
Accelerating String Set Matching in FPGA Hardware for Bioinformatics Research
Background: This paper describes techniques for accelerating the performance of the string set matching problem with particular emphasis on applications in computational proteomic...
Yoginder S. Dandass, Shane C. Burgess, Mark Lawren...