93 search results - page 17 / 19 » Timing optimization of FPGA placements by logic replication |
FPGA
2010
ACM
15 years 6 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
ESCIENCE
2007
IEEE
15 years 3 months ago
2007
IEEE
The emergence of computational grids has lead to an increased reliance on task schedulers that can guarantee the completion of tasks that are executed on unreliable systems. There...
ISPASS
2006
IEEE
15 years 3 months ago
2006
IEEE
— Due to the long simulation times of the reference input sets, microarchitects resort to alternative techniques to speed up cycle-accurate simulations. However, the reduction in...
DAC
2006
ACM
15 years 10 months ago
2006
ACM
Transistor leakage is poised to become the dominant source of power dissipation in digital systems, and reconfigurable devices are not immune to this problem. Modern FPGAs already...
DAC
2003
ACM
15 years 10 months ago
2003
ACM
Delay budget is an excess delay each component of a design can tolerate under a given timing constraint. Delay budgeting has been widely exploited to improve the design quality. W...