93 search results - page 8 / 19 » Timing optimization of FPGA placements by logic replication |
93
Voted
DATE
2000
IEEE
15 years 2 months ago
2000
IEEE
Novel methodology and algorithms to seamlessly integrate logic synthesis and physical placement through a transformational approach are presented. Contrary to most placement algor...
FPL
2009
Springer
15 years 2 months ago
2009
Springer
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...
77
Voted
IPPS
2005
IEEE
15 years 3 months ago
2005
IEEE
Secret sharing algorithms have been used for intrusion tolerance, which ensure the confidentiality, integrity and availability of critical information. However, dynamically changi...
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
— The paper introduces novel field programmable gate array (FPGA) circuits based on hybrid CMOS/resistive switching device (memristor) technology and explores several logic archi...
FPL
2005
Springer
15 years 3 months ago
2005
Springer
This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has comple...