188 search results - page 21 / 38 » Timing-driven optimization using lookahead logic circuits |
114
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FPGA
2004
ACM
15 years 5 months ago
2004
ACM
The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...
FPL
2008
Springer
15 years 1 months ago
2008
Springer
This paper presents a fast and scalable method of computing signal toggle rate in FPGA-based circuits. Our technique is a vectorless estimation technique, which can be used in a C...
ICCAD
2006
IEEE
15 years 8 months ago
2006
IEEE
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
100
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ICCAD
1999
IEEE
15 years 4 months ago
1999
IEEE
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ens...
ISMVL
2010
IEEE
15 years 3 months ago
2010
IEEE
—Using EXOR gates in logic synthesis often results in smaller circuit realizations. While in AND/OR synthesis the problem definition is clear, in AND/EXOR synthesis several clas...