188 search results - page 24 / 38 » Timing-driven optimization using lookahead logic circuits |
170
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DAC
2001
ACM
16 years 6 months ago
2001
ACM
In this paper, we present a new technique for the e cient dynamic detection and removal of inactive clauses, i.e. clauses that do not a ect the solutions of interest of a Boolean ...
179
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ISQED
2005
IEEE
15 years 11 months ago
2005
IEEE
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
162
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ISVLSI
2007
IEEE
16 years 2 days ago
2007
IEEE
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of e...
191
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VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...
194
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CEC
2011
IEEE
14 years 5 months ago
2011
IEEE
—Constrained Genetic Programming (CGP) is a method of searching the Genetic Programming search space non-uniformly, giving preferences to certain subspaces according to some heur...