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» Timing-driven optimization using lookahead logic circuits
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79
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FPGA
1998
ACM
140views FPGA» more  FPGA 1998»
15 years 3 months ago
More Wires and Fewer LUTs: A Design Methodology for FPGAs
In designing FPGAs, it is important to achieve a good balance between the number of logic blocks, such as Look-Up Tables (LUTs), and wiring resources. It is dicult to nd an optim...
Atsushi Takahara, Toshiaki Miyazaki, Takahiro Muro...
82
Voted
FPL
2009
Springer
86views Hardware» more  FPL 2009»
15 years 4 months ago
Improving logic density through synthesis-inspired architecture
We leverage properties of the logic synthesis netlist to define both a logic element architecture and an associated technology mapping algorithm that together provide improved lo...
Jason Helge Anderson, Qiang Wang
DATE
1999
IEEE
123views Hardware» more  DATE 1999»
15 years 4 months ago
An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length
Different logic synthesis tasks have been formulated as input encoding problems but restricted to use a minimum number of binary variables. This paper presents an original column ...
Manuel Martínez, Maria J. Avedillo, Jos&eac...
SAT
2010
Springer
141views Hardware» more  SAT 2010»
15 years 3 months ago
Synthesizing Shortest Linear Straight-Line Programs over GF(2) Using SAT
Non-trivial linear straight-line programs over the Galois field of two elements occur frequently in applications such as encryption or high-performance computing. Finding the shor...
Carsten Fuhs, Peter Schneider-Kamp
FPGA
2008
ACM
184views FPGA» more  FPGA 2008»
15 years 1 months ago
Mapping for better than worst-case delays in LUT-based FPGA designs
Current advances in chip design and manufacturing have allowed IC manufacturing to approach the nanometer range. As the feature size scales down, greater variability is experience...
Kirill Minkovich, Jason Cong