188 search results - page 29 / 38 » Timing-driven optimization using lookahead logic circuits |
79
Voted
ISQED
2007
IEEE
15 years 6 months ago
2007
IEEE
This paper studies the impact of variability on the noise robustness of logic gates using noise rejection curves (NRCs). NRCs allow noise pulses to be modeled using magnitude-dura...
GECCO
2003
Springer
15 years 4 months ago
2003
Springer
This poster paper summarizes our research on fault tolerance arising as a by-product of the evolutionary computation process. Past research has shown evidence of robustness emergin...
100
Voted
ISLPED
2005
ACM
15 years 5 months ago
2005
ACM
This work first presents an analytical repeater insertion method which optimizes power under delay constraint for a single net. This method finds the optimal repeater insertion ...
101
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ICCAD
2006
IEEE
15 years 8 months ago
2006
IEEE
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...
93
Voted
VLSID
2009
IEEE
16 years 8 days ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...