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» Timing-driven optimization using lookahead logic circuits
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ISQED
2008
IEEE
186views Hardware» more  ISQED 2008»
15 years 6 months ago
Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems
—Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic Voltage Scheduling (DVS) has been provably one of t...
Foad Dabiri, Navid Amini, Mahsan Rofouei, Majid Sa...
GECCO
2004
Springer
134views Optimization» more  GECCO 2004»
15 years 5 months ago
A New Universal Cellular Automaton Discovered by Evolutionary Algorithms
In Twenty Problems in the Theory of Cellular Automata, Stephen Wolfram asks “how common computational universality and undecidability [are] in cellular automata.” This papers p...
Emmanuel Sapin, Olivier Bailleux, Jean-Jacques Cha...
GECCO
2009
Springer
130views Optimization» more  GECCO 2009»
15 years 6 months ago
Liposome logic
VLSI research, in its continuous push toward further miniaturisation, is seeking to break through the limitations of current circuit manufacture techniques by moving towards biomi...
James Smaldon, Natalio Krasnogor, Alexander Camero...
DAC
2007
ACM
16 years 19 days ago
Global Critical Path: A Tool for System-Level Timing Analysis
An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is...
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea...
ICCAD
2008
IEEE
138views Hardware» more  ICCAD 2008»
15 years 8 months ago
Fault tolerant placement and defect reconfiguration for nano-FPGAs
—When manufacturing nano-devices, defects are a certainty and reliability becomes a critical issue. Until now, the most pervasive methods used to address reliability, involve inj...
Amit Agarwal, Jason Cong, Brian Tagiku