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» Timing-driven placement by grid-warping
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DAC
2004
ACM
15 years 11 months ago
Quadratic placement using an improved timing model
The performance of timing-driven placement methods depends strongly on the choice of the net model. In this paper a more precise net model is presented that does not increase nume...
Bernd Obermeier, Frank M. Johannes
191
Voted
ICCAD
1995
IEEE
106views Hardware» more  ICCAD 1995»
15 years 11 months ago
Re-engineering of timing constrained placements for regular architectures
In a typical design ow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design speci cation either as a result o...
Anmol Mathur, K. C. Chen, C. L. Liu
170
Voted
ASPDAC
2005
ACM
92views Hardware» more  ASPDAC 2005»
15 years 9 months ago
An LP-based methodology for improved timing-driven placement
— A method for timing driven placement is presented. The core of the approach is optimal timing-driven relaxed placement based on a linear programming (LP) formulation. The formu...
Qingzhou (Ben) Wang, John Lillis, Shubhankar Sanya...
GLVLSI
2000
IEEE
110views VLSI» more  GLVLSI 2000»
15 years 12 months ago
A sensitivity based placer for standard cells
We present a new timing driven method for global placement. Our method is based on the observation that similar net length reductions in the different nets that make up a path may...
Bill Halpin, C. Y. Roger Chen, Naresh Sehgal
FPL
2005
Springer
114views Hardware» more  FPL 2005»
16 years 1 months ago
Post-Placement BDD-Based Decomposition for FPGAs
This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has comple...
Valavan Manohararajah, Deshanand P. Singh, Stephen...