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» Timing-driven placement for FPGAs
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98
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GLVLSI
2000
IEEE
105views VLSI» more  GLVLSI 2000»
15 years 6 months ago
An evolutionary approach to timing driven FPGA placement
: We propose a novel evolutionary approach to the problem of timing-driven FPGA placement. The method used is evolutionary programming (EP) with incremental position encoded in the...
R. Venkatraman, Lalit M. Patnaik
85
Voted
DAC
2004
ACM
16 years 2 months ago
Efficient timing closure without timing driven placement and routing
Miodrag Vujkovic, David Wadkins, William Swartz, C...
87
Voted
DAC
1995
ACM
15 years 5 months ago
Timing Driven Placement for Large Standard Cell Circuits
William Swartz, Carl Sechen
124
Voted
FPGA
1999
ACM
115views FPGA» more  FPGA 1999»
15 years 6 months ago
Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density
In this paper, we investigate the speed and area-efficiency of FPGAs employing “logic clusters” containing multiple LUTs and registers as their logic block. We introduce a ne...
Alexander Marquardt, Vaughn Betz, Jonathan Rose
118
Voted
FPL
2004
Springer
90views Hardware» more  FPL 2004»
15 years 7 months ago
Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis
Abstract. Layout tools for FPGAs can typically be run in two different modes: non-timing-driven and timing-driven. Non-timing-driven mode produces a solution quickly, without consi...
Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, ...