484 search results - page 52 / 97 » To Parallelize or Not to Parallelize, Speed Up Issue |
ISCA
1997
IEEE
15 years 2 months ago
1997
IEEE
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, ...
HPCA
2007
IEEE
15 years 10 months ago
2007
IEEE
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...
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DMG
2005
Springer
15 years 4 months ago
2005
Springer
Grid services provide an important abstract layer on top of heterogeneous components (hardware and software) that take part into a grid environment. We are developing a data grid s...
SIGGRAPH
2000
ACM
15 years 2 months ago
2000
ACM
Pomegranate is a parallel hardware architecture for polygon rendering that provides scalable input bandwidth, triangle rate, pixel rate, texture memory and display bandwidth while...
IPPS
1999
IEEE
15 years 2 months ago
1999
IEEE
Existing low-latency protocols make unrealistically strong assumptions about reliability. This allows them to achieve impressive performance, but also prevents this performance bei...