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151
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CCR
2006
92views more  CCR 2006»
15 years 3 months ago
Flow labelled IP over ATM: design and rationale
We describe a system in which layer 2 switching is placed directly under the control of layer 3 routing protocols on a hop-by-hop basis. Specifically, ATM switching is controlled ...
Greg Minshall, Robert M. Hinden, Eric Hoffman, Fon...
132
Voted
CONNECTION
2004
134views more  CONNECTION 2004»
15 years 3 months ago
'Feeling' the flow of time through sensorimotor co-ordination
In this paper, we aim to design decision-making mechanisms for a simulated Khepera robot equipped with simple sensors, which integrates over time its perceptual experience in order...
Elio Tuci, Vito Trianni, Marco Dorigo
184
Voted
VLSID
2007
IEEE
231views VLSI» more  VLSID 2007»
16 years 4 months ago
AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs
We present AHIR, an intermediate representation (IR), that acts as a transition layer between software compilation and hardware synthesis. Such a transition layer is intended to t...
Sameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya, Ma...
121
Voted
DAC
1998
ACM
15 years 8 months ago
Rate Optimal VLSI Design from Data Flow Graph
This paper considers the rate optimal VLSI design of a recursive data flow graph (DFG). Previous research on rate optimal scheduling is not directly applicable to VLSI design. We ...
Moonwook Oh, Soonhoi Ha
138
Voted
BPSC
2010
139views Business» more  BPSC 2010»
15 years 1 months ago
Static Information Flow Analysis of Workflow Models
: This paper proposes a framework for the detection of information leaks in workflow descriptions based on static information flow analysis. Despite the correct deployment of acces...
Rafael Accorsi, Claus Wonnemann