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ISCA
1998
IEEE
114views Hardware» more  ISCA 1998»
15 years 6 months ago
The MIT Alewife Machine: Architecture and Performance
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a scalable and cost-effective mesh network at a constant cost per node. The MIT Al...
Anant Agarwal, Ricardo Bianchini, David Chaiken, K...
110
Voted
SNPD
2003
15 years 3 months ago
Incomplete Information Processing for Optimization of Distributed Applications
This paper focuses on non-strict processing, optimization, and partial evaluation of MPI programs which use incremental data structures (ISs). We describe the design and implement...
Alfredo Cristóbal-Salas, Andrei Tchernykh, ...
DSN
2003
IEEE
15 years 7 months ago
A Preemptive Deterministic Scheduling Algorithm for Multithreaded Replicas
Software-based active replication is expensive in terms of performance overhead. Multithreading can help improve performance; however, thread scheduling is a source of nondetermin...
Claudio Basile, Zbigniew Kalbarczyk, Ravishankar K...
ISCA
1995
IEEE
118views Hardware» more  ISCA 1995»
15 years 5 months ago
The EM-X Parallel Computer: Architecture and Basic Performance
Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor ...
Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Ha...
ISCA
2011
IEEE
238views Hardware» more  ISCA 2011»
14 years 5 months ago
Rebound: scalable checkpointing for coherent shared memory
As we move to large manycores, the hardware-based global checkpointing schemes that have been proposed for small shared-memory machines do not scale. Scalability barriers include ...
Rishi Agarwal, Pranav Garg, Josep Torrellas