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» Tolerating Hard Faults in Microprocessor Array Structures
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JPDC
2006
111views more  JPDC 2006»
14 years 9 months ago
Designing irregular parallel algorithms with mutual exclusion and lock-free protocols
Irregular parallel algorithms pose a significant challenge for achieving high performance because of the difficulty predicting memory access patterns or execution paths. Within an...
Guojing Cong, David A. Bader
IOLTS
2008
IEEE
102views Hardware» more  IOLTS 2008»
15 years 3 months ago
Integrating Scan Design and Soft Error Correction in Low-Power Applications
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
Michael E. Imhof, Hans-Joachim Wunderlich, Christi...
70
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SIGMETRICS
2008
ACM
121views Hardware» more  SIGMETRICS 2008»
14 years 9 months ago
Disk scrubbing versus intra-disk redundancy for high-reliability raid storage systems
Two schemes proposed to cope with unrecoverable or latent media errors and enhance the reliability of RAID systems are examined. The first scheme is the established, widely used d...
Ilias Iliadis, Robert Haas, Xiao-Yu Hu, Evangelos ...
ISCA
2010
IEEE
340views Hardware» more  ISCA 2010»
15 years 2 months ago
Necromancer: enhancing system throughput by animating dead cores
Aggressive technology scaling into the nanometer regime has led to a host of reliability challenges in the last several years. Unlike onchip caches, which can be efficiently prot...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
MICRO
2009
IEEE
160views Hardware» more  MICRO 2009»
15 years 4 months ago
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor
Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular and dense structures...
Bo Zhao, Yu Du, Youtao Zhang, Jun Yang 0002