48 search results - page 8 / 10 » Tolerating data access latency with register preloading |
PLDI
1999
ACM
15 years 2 months ago
1999
ACM
Hardware trends have produced an increasing disparity between processor speeds and memory access times. While a variety of techniques for tolerating or reducing memory latency hav...
CDC
2008
IEEE
15 years 4 months ago
2008
IEEE
Abstract— In this paper, we consider the problem of stabilizing sufficiently smooth nonlinear time-invariant plants over a network whereby feedback is closed through a limitedba...
HIPEAC
2009
Springer
15 years 1 months ago
2009
Springer
Abstract. Exposing more instruction-level parallelism in out-of-order superscalar processors requires increasing the number of dynamic in-flight instructions. However, large instru...
HPCA
2004
IEEE
15 years 10 months ago
2004
IEEE
Modern out-of-order processors tolerate long latency memory operations by supporting a large number of inflight instructions. This is particularly useful in numerical applications...
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ISCAPDCS
2004
14 years 11 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...