39 search results - page 5 / 8 » Tolerating node failures in cache only memory architectures |
139
Voted
CASES
2003
ACM
15 years 8 months ago
2003
ACM
Recent research in sensor networks has raised issues of security for small embedded devices. Security concerns are motivated by the deployment of a large number of sensory devices...
122
Voted
SRDS
2007
IEEE
15 years 10 months ago
2007
IEEE
Fault tolerant distributed protocols typically utilize a homogeneous fault model, either fail-crash or fail-Byzantine, where all processors are assumed to fail in the same manner....
114
Voted
ACSAC
2008
IEEE
15 years 10 months ago
2008
IEEE
Main memory contains transient information for all resident applications. However, if memory chip contents survives power-off, e.g., via freezing DRAM chips, sensitive data such a...
155
Voted
ASWSD
2004
Springer
15 years 9 months ago
2004
Springer
– A safety-critical real-time computer system must provide its services with a dependability that is much better than the dependability of any one of its constituent components. ...
108
Voted
IPPS
1999
IEEE
15 years 8 months ago
1999
IEEE
In this paper we propose a simple extension to the I/O architecture of scalable multiprocessors that optimizes page swap-outs significantly. More specifically, we propose the use o...